RECENT PUBLICATIONS

Student Dissertations:

1. Bendik Kleveland, "CMOS Interconnects Beyond 10 GHz," August 2000.

2. Theerachet Soorapanth, "CMOS RF Filtering at GHz Frequency," August 2002.

3. Richard Chang, "Near Speed-of-Light On-Chip Electrical Interconnects," November 2002.

4. Frank O'Mahony, "10 GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators," August 2003.

5. Dae-Yong Kim, "Study on Reliability of VLSI Interconnection Structures," December 2003.

6. Niranjan Talwalkar, "Integrated CMOS Transmit-Receive Switch Using On-Chip Spiral Inductors," December 2003.

7. So Young Kim, "Modeling and Screening On-Chip Interconnect Inductance," July 2004.

8. Haitao Gan, "On-Chip Transformer Modeling, Characterization, and Applications in Power and Low Noise Amplifiers; March 2006.

Journal Articles:

7. M. Asheghi, M. Touzelbaev, K. Goodson, Y. Leung and S. Wong, "Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates," ASME Journal of Heat Transfer, Vol. 120, pp. 1-7, February 1998.

8. S. Kuehne, A. Chan, C. Nguyen and S. Wong, "SOI MOSFET with Buried Body Strap by Wafer Bonding," IEEE Transactions on Electron Devices, Vol. 45, pp. 1084-1091, May 1998.

9. C. Yue and S. Wong, "On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's," IEEE Journal of Solid State Circuits, Vol. 33, pp. 743-752, May 1998.

10. A. Loke, J. Wetzel, J. Stankus, M. Angyal, B. Mowry and S. Wong, "Electrical Leakage at Low-K polyimide/TEOS Interface, " IEEE Electron Device Letters, Vol. 19, pp. 177-179, June 1998

11. W. Chan, J. Sin and S. Wong, "A Novel Crosstalk Isolation Structure for Bulk CMOS Power IC's," IEEE Transactions on Electron Devices, Vol. 45, pp. 1580-1586, July 1998.

12. Y. Leung, A. Paul, J. Plummer and S. Wong, "Lateral IGBT in Thin SOI for High Voltage, High Speed Power IC," IEEE Transactions on Electron Devices, Vol. 45, pp. 2251-2254, October 1998.

13. C-M Zetterling, M. Ostling, C. Harris, P. Wood and S.Wong, "UV-Ozone Precleaning and Forming Gas Annealing Applied to Wet Thermal Oxidation of P-Type Silicon Carbide," Materials Science in Semiconductor Processing, Vol. 2, pp. 23-27, 1999.

14. C. Ryu, H. Lee, K. Kwon, A. Loke and S. Wong, "Barriers for Copper Interconnections," Solid State Technology, Vol. 42, pp. 53-56, April 1999.

15. C. Ryu, K. Kwon, A. Loke, H. Lee, T. Nogami, V. Dubin, R. Kavari, G. Ray and S. Wong, "Microstructure and Reliability of Copper Interconnects," IEEE Transactions on Electron Devices, Vol. 46, pp. 1113-1120, June 1999.

16. M. Zargari, J. Leung, S. Wong and B. Wooley, "A BiCmos Active Substrate Probe-Card technology for Digital testing," IEEE Journal of Solid State Circuits, Vol. 34, pp. 1118-1135, August 1999.

17. A. Loke, J. Wetzel, P. Townsend, T. Tanabe, R. Vrtis, M. Zussman, D. Kumar, C. Ryu, and S. Wong, "Kinetics of Copper Drift in Low-k Polymer Interlevel Dielectrics," IEEE Transactions on Electron Devices, Vol. 46, pp. 2178-2187, November 1999.

18. C. Yue and S. Wong, "Physical Modeling of Spiral Inductors on Silicon," IEEE Transactions on Electron Devices, Vol. 47, pp. 560-568, March 2000.

19. B. Kleveland, T. Maloney, I. Morgan, L. Madden, T. Lee and S. Wong, "Distributed ESD Protection for High-Speed Integrated Circuits," IEEE Electron Device Letters, Vol. 21, pp. 390-392, August 2000.

20. T. Lee and S. Wong, "CMOS RF Integrated Circuits at 5 GHz and Beyond," Proceedings of IEEE, Vol. 88, pp. 1560-1571, October 2000.

21. B. Kleveland, C. Diaz, D. Vook, L. Madden, T. Lee and S. Wong, "Exploring CMOS Reverse Interconnect Scaling in Multigigahertz Amplifier and Oscillator Design," IEEE Journal of Solid State Circuits, Vol. 36, pp. 1480-1488, October 2001.

22. T. Soorapanth and S. Wong, "A 0-db IL 2140+30 MHz Bandpass Filter Utilizing Q-Enhanced Spiral Inductors in Standard CMOS," IEEE Journal of Solid State Circuits, Vol. 37, pp. 579-586, May 2002.

23. B. Kleveland, X Qi, L. Madden, T. Furusawa, R. Dutton, M. Horowitz and S. Wong, "High Frequency Characterization of On-Chip Digital Interconnects," IEEE Journal of Solid State Circuits, Vol. 37, pp. 716-725, June 2002.

24. H. Lee, S. Wong and S. Lopatin, "Correlation of Stress and Texture Evolution During Self- and Thermal Annealing of Electroplated Cu Films," Journal of Applied Physics, Vol. 93, pp. 3796-3804, April 2003.

25. R. Chang, N. Talwalkar, C. Yue and S. Wong, "Near Speed-of-Light Signaling over On-Chip Electrical Interconnects," IEEE Journal of Solid State Circuits, Vol. 38, pp. 834-838, May 2003.

26. F. O'Mahony, C. Yue, M. Horowitz and S. Wong, "A 10-GHz Global Clock Distribution Using Coupled Standing Wave Oscillators," IEEE Journal of Solid State Circuits, Vol. 38, pp. 1813-1820, Nov 2003.

27. R. Chang, M. Yang, P. Ho, Y. Wang, Y Chia, B. Liew, C. Yue and S. Wong, "Modeling and Optimization of Substrate Resistance for RF-CMOS," IEEE Transactions on Electron Devices, Vol. 51, pp. 421-426, March 2004.

28. N. Talwakar, C. Yue, G. Gan and S. Wong, "Integrated CMOS Transmit-Receive Switch Using L-C Tuned Substrate Bias for 2.4-GHz and 5.2-GHz Applications," IEEE Journal of Solid State Circuits, Vol. 39, pp. 863 -870, June 2004.

Invited Presentations:

29. S. Wong, A. Loke, J. Wetzel, P. Townsend, R. Vrtis, and M. Zussman, "Electrical Reliability of Copper and Low-K Dielectric Integration," Materials Research Society Spring Meeting, E7.1, San Francisco, CA, April 1998.

30. S. Wong, C. Ryu, H. Lee and K. Kwon, "Barriers for Copper Interconnections," Materials Research Society Spring Meeting, I2.3, San Francisco, CA, April 1998.

31. S. Wong, C. Ryu, H. Lee, A. Loke, K. Kwon, S. Bhattacharya, R. Eaton, R. Faust, R. Mikkola, J. Mucha, J. Ormando, "Barrier/Seed Layer Requirements for Copper Interconnects, " IEEE International Interconnect Conference, pp. 107-109, Burlingame, CA, June 1998.

32. S. Wong, H. Lee, C. Ryu, A. Loke, K. Kwon, "Effects of Barrier/Seed Layer on Copper Microstructure, " Advanced Metallization Conference, pp. 53-54, Tokyo, Japan, September 1998.
33. S. Wong " Cu Deposition Methods and Film Properties, Thin Film Users' Group Annual Symposium, Foster City, CA, October 1998.

34. S. Wong, H. Lee, C. Ryu, A. Loke, K. Kwon, "Effects of Microstructure on Cu Electromigration, " SRC Topical Research Conference on Reliability, Austin, TX, October 1998.

35. S. Wong, "Modeling of RF Inductors," IEEE Solid State Circuits Technology Workshopon RF Passive Components, San Francisco, CA, February 1999.

36. S. Wong, "Copper Interconnect Technology," Electrochemical Chemical Society Santa Clara Chapter Meeting, Santa Clara, CA, March 1999.

37. A. Loke, S. Wong, N. Talwalkar, J. Wetzel, P. Townsend, T. Tanabe, R. Vrtis, M. Zussman, and D. Kumar, "Evaluation of Copper Penetration in Low-K Polymer Dielectrics Using Bias-Temperature Stress," Materials Research Society Spring Meeting, O4.4, San Francisco, CA, April 1999.

38. C.P. Yue and S.S. Wong, "Design strategy of on-chip inductors for highly integrated RF systems," Design Automation Conference Proceedings, pp. 982-987, June 1999.

39. S. Wong, H. Lee, D. Kim and K. Kwon "Microstructure of Barrier / Copper Interface," SRC Topical Research Conference on Reliability, Stanford, CA, October 2000.

40. N. Talwalkar, C. Yue and S. Wong, "Compact Modeling of High Frequency Phenomena for On-Chip Spiral Inductors", Workshop on Compact Modeling, San Francisco, CA, February 2003.

41. S. Wong, P. Yue, R. Chang, S. Kim, B. Kleveland and F. O'Mahony, "On-Chip Interconnect Inductance ­ Friend or Foe", International Symposium on Quality Electronic Design, pp. 389-394, San Jose, CA, March 2003.

42. F. O'Mahony, C. Yue, M. Horowitz and S. Wong, "Design of a 10GHz Clock Network Using Coupled Standing-Wave Oscillators," Design Automation Conference Proceedings, pp. 682-687, June 2003.

Conference Proceedings:

43. V. Dubin, S. Chen, R. Cheung, C. Ryu and S. Wong, "Copper Electroplating for Damascene ULSI Interconnects," Materials Research Society Spring Meeting, I7.3, San Francisco, CA, April 1998.

44. A. Loke, J. Wetzel, C. Ryu, W. Lee and S. Wong, "Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization," Symposium on VLSI Technology Digest of Technical Papers, pp. 26-27, Honolulu, Hawaii, June 1998.

45. C. Ryu, K. Kwon, A. Loke, V. Dubin, R. Kavari, G. Ray and S. Wong, "Electromigration of Submicron Damascene Copper," Symposium on VLSI Technology Digest of Technical Papers, pp. 156-157, Honolulu, Hawaii, June 1998.

46. T. Soorapanth, C. Yue, D. Shaeffer, T. Lee and S. Wong, "Analysis and Optimization of Accumulation-Mode Varactor for RF ICs," Symposium on VLSI Circuits Digest of Technical Papers, pp. 32-33, Honolulu, Hawaii, June 1998.

47. B. Kleveland, S. Wong and T. Lee, "50 Ghz Interconnect Design in Standard Silicon Technology," IEEE MTT-S International Microwave Symposium, pp. 1913-1916, Baltimore, MD, June 1998.

48. A. Loke, J. Wetzel, C. Ryu, and S. Wong, "Copper Drift in Low-K Polymer Dielectrics for ULSI Metallization," SRC TECHCON, Las Vegas, NV, September 1998.

49. Y. Zhao, A. Huang, Y. Leung and S. Wong. "Lateral Emitter Controlled Thyristor (LECT) on SOI," IEEE International SOI Conference, October 1998.

50. H. Lee, S. Lopatin, T. Nogami, and S. Wong, "Effect of Seed Layer Texture and Surface Roughness on the Microstructure of Electroplated Copper Film," Materials Research Society Fall Meeting, Symposium A, A1.9, Boston, MA, December 1998.

51. S. Mohan, C. Yue, M. Mar Hershenson, S. Wong and T. Lee,"Modeling and Characterization of On-Chip Transformer" International Electron Devices Meeting Technical Digest, pp. 531-534, San Francisco, CA, December 1998.

52. B. Kleveland, C. Diaz, D. Vook, L. Madden, T. Lee and S. Wong, "Monolithic CMOS Distributed Amplifier and Oscillator," International Solid State Circuits Conference Digest of Technical Papers, pp. 70-71, San Francisco, CA, February 1999.

53. C. Yue and S. Wong, "A Study on Substrate Effects of Silicon-Based RF Passive Components," International Microwave Symposium Digest, pp. 1625-1628, Los Angeles, CA, June 1999.

54. H. Lee, S. Lopatin, D. Kim, V. Dubin and S. Wong, "Effects of Plating Current Density and Solution Additive on the Microstructure and Recrystallization Rate of Electroplated Copper Films," Proceedings of Advanced Metallization for ULSI Applications, October 1999.

55. B. Kleveland, X. Qi, L. Madden, R. Dutton and S. Wong, "Line Inductance Extraction and Modeling in a Real Chip with Power Grid," International Electron Devices Meeting Technical Digest, pp. 901-904, Washington, DC, December 1999.

56. X. Qi, B. Kleveland, Z. Yu, S. Wong and R. Dutton, "On-Chip Inductance Modeling of VLSI Interconnects," International Solid State Circuits Conference Digest of Technical Papers, pp. 172-173, San Francisco, CA, February 2000.

57. K. Banerjee, A. Mehrota, W. Hunter, K. Saraswat, S. Wong and K. Goodson, "Microanalysis of VLSI Interconnect Failure Modes under Short-Pulse Stress Conditions," IEEE International Reliability Physics Symposium Proceedings, pp. 283-288, San Jose, CA, April 2000.

58. K. Banerjee, D. Kim, A. Amerasekera, C. Hu, K. Goodson and S. Wong, "Quantitative Projections of Reliability and Performance for Low-k/Cu Interconnect Systems," IEEE International Reliability Physics Symposium Proceedings, pp. 354-358, San Jose, CA, April 2000.

59. H. Lee, S. Lopatin and S. Wong, "Correlation of Stress and Texture Evolution During Self- and Thermal Annealing of Electroplated Cu Films," IEEE International Interconnect Conference, pp. 114-116, Burlingame, CA, June 2000.

60. H. Lee, S.. Lopatin, A. Marshall, and S. Wong, "Evidence of Dislocation Loops as a Driving Force for Self Annealing in Electroplated Cu Films", IEEE International Interconnect Technology Conference, pp. 236-238, Burlingame, CA, June 2001.

61. T. Soorapanth and S. Wong, "A 0dB-IL, 2140+/-30MHz Bandpass Filter Utilizing Q-Enhanced Spiral Inductors in Standard CMOS," Symposium on VLSI Circuits Digest of Technical Papers, pp. 15-18, Kyoto, Japan, June 2001.

62. Y. Sun, Z. Peng, D. Kim, K. Goodson and S. Wong, "Recovery of Open Via after Electromigration in Cu Dual Damascene Interconnect," IEEE International Reliability Physics Symposium Proceedings, pp. 435-436, Dallas, TX, April 2002.

63. R. Chang, C. Yue and S. Wong, "Near Speed-of-Light On-Chip Electrical Interconnect," Symposium on VLSI Circuits Digest of Technical Papers, pp. 18-21, Honolulu Hawaii, June 2002.

64. N. Talwalkar, C. Yue and S. Wong, "An Integrated 5.2GHz CMOS T/R Switch with LC-Tuned Substrate Bias," International Solid State Circuits Conference Digest of Technical Papers, pp. 362-363, San Francisco, CA, February 2003.

65. F. O'Mahony, C. Yue and S. Wong, "10GHz Clock Distribution Using Coupled Standing-Wave Oscillators," International Solid State Circuits Conference Digest of Technical Papers, pp. 428-429, San Francisco, CA, February 2003.

66. S. Kim, Y. Massoud and S. Wong, "On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1mm Technology and Beyond", International Symposium on Quality Electronic Design, pp. 401-404, San Jose, CA, March 2003.

67. D. Kim and S. Wong, "Mechanism for Early Failure in Cu Dual Damascene Structure", IEEE International Interconnect Technology Conference, pp. 265-267, Burlingame, CA, June 2003.