The research in my group bridges the technology and design issues of high-speed integrated circuits. The various projects concentrate on understanding and overcoming the performance limiting factors in devices, interconnections and packages. See recent publications for current emphasis.
Device Technology
Somnuk
Ratanaphanyarat (PhD 89, currently with TSMC, San Jose, CA)
Sophie
Verdonckt-Vanderbroek
(PhD 90, currently with Xerox, Webster,
NY)
Cuong
Nguyen (PhD 93, currently with ACTgent, Selanger, Malaysia)
Stephen
Kuehne (PhD 96, currently with Agere, Minneapolis, MN)
No current student
The switching
speed of today's devices is limited not only by the carrier transit
time, but more importantly, also by the parasitic capacitors and
resistors. In this project, we develop and model novel transistor
structures for high-speed applications such as RF communications.
Our emphasis is on using advanced processing technologies to significantly
reduce parasitic elements.
SOI Power Device and Process
Ying-Keung
Leung (PhD 97, currently with TSMC, Taiwan)
No current student
The integration of power devices with digital and analog electronics promises to revolutionize the power control industry and other related applications. This project explores the performance advantages (breakdown voltage, on resistance, and switching speed) of power devices fabricated on SOI, and develops various processing technologies (e.g., wafer bonding) which are essential to power integrated circuits.
Multilevel Interconnection
Technology
Dave Thomas(PhD
90, currently with IBM Essex Junction, VT)
Victor Lee(PhD
91, currently with IBM, Boston, MA)
Ho
Kang (PhD
93, currently with Samsung, Korea)
James
Cho (PhD
94, currently with Atheros Communications, Sunnyvale, CA)
Changsup Ryu (PhD
98, currently with Samsung, Korea)
Alvin
Loke (PhD 99, currently with Agilent, Fort Collins, CO)
Haebum
Lee (PhD 01, currently with Intel, Santa Clara, CA)
Dae-Yong
Kim (PhD 03)
No current student
Interconnection is a critical factor that limits the performance and reliability of today's integrated circuits. The commonly used aluminum alloy is not expected to meet the future requirements. In this project, we develop the technology, and characterize the physical and electrical behavior of multilevel copper interconnections. Emphasis is on chemical vapor deposition and electroplating techniques. The integration of Cu interconnections with various low-K dielectrics is also under investigation.
Interconnection Design
Patrick
Yue (PhD 98, currently with Carnegie Mellon University, Pittsburgh,
PA)
Bendik
Kleveland (PhD 00, currently with Matrix Semiconductor, CA)
Theerachet
Soorapanth (PhD 02, currently with National Electronic
and Computer Technology Center, Thailand)
Richard
Chang (PhD 02, currently with Atheros Communications, Santa Clara, CA>
Frank
Kolor (PhD 03, currently with Intel, Hillsboro,
OR)
Niranjan
Talwalkar (PhD 03, currently with IRF Semiconductor,
CA)
So-Young
Kim (PhD 04, currently with Intel, Santa Clara, CA)
Haitao
Gan (PhD 06, currently with Atheros Communications, Santa Clara, CA)
Paul
Park (phpark@stanford.edu)
Yun
Bai (baiyun@stanford.edu)
Andrew
Poon (megapoon@stanford.edu)
As multiple levels of interconnections are packed in ever-closer proximity, the electromagnetic interactions become significant and affect signal propagation and integrity. Furthermore, at above GHz, high-frequency effects (skin depth, dielectric and substrate losses, etc.) are no longer negligible. In this project, the characteristics of copper and low-K dielectrics at above GHz frequencies are studied. Appropriate models are developed for predicting the high-frequency performance of advanced multilevel interconnection network. The applications of advanced metallization technology to fabricate critical elements such as inductors, transformers and strip-lines for RF communication circuits are being studied. Novel design concepts to extend the operational frequency of integrated circuits are also being explored.
3D IC
Wei Wang (mailvv@stanford.edu)
Aaron
Gibby (agibby@stanford.edu)
Prof. Wong is the principal investigator of a DARPA sponsored project on 3-dimensional integrated circuits. This project involves over 10 faculty members. The overall goals are to
Demonstrate
and quantify the performance advantages of 3D IC;
Develop key technology modules that enable monolithic 3D integration;
and
Develop an efficient heat removal strategy.
Multichip Module Technology
Mark
Beiley (PhD 93, currently with Intel, Chandler, AZ)
Wheling Cheng (PhD
95)
Justin Leung
(PhD 97, currently with Intel, Santa Clara, CA)
No current student
On and off chip data transmission is a bottleneck of communication in many high speed systems. In this project, we study the utilization of multichip module technology to eliminate the packages and reduce the spatial distances between chips. Testing of the bare chips before they are mounted on the module is widely regarded as the most critical problem plaguing the adoption of the technology. Our present emphasis is to develop an active array probe card technology for high speed and high resolution testing of integrated circuits that have a large number of input/output pads.
Optical Interconnection
Abbas Behfar-Rad (PhD
90, currently with BinOptics, Ithaca, NY)
Steve
Biellak (PhD 95, currently with Teleoptics)
No current student
Optical interconnection is expected to play a major role in data communication within and between chips. This project aims at developing GaAs/AlGaAs lasers and appropriate interfacing techniques to achieve optical interconnections between chips. The work emphasizes the monolithic fabrication of laser structures.
Wafer Scale DSP System
Jaehee
You (PhD
90, currently with Hongik University, Seoul, Korea)
No current student
In this project, a pipelined digital signal processing system is designed with systolic array approach for multichip module.