The research in my group bridges the technology and design issues of high speed integrated systems. The various projects concentrate on the development of technologies which overcome the performance limiting factors in devices, interconnections and packages. Current emphasis is on advanced materials and performance estimation of interconnections. See recent publications for more details.
Multichip Module Technology | Optical Interconnects | Wafer Scale DSP System
Device Technology
Somnuk Ratanaphanyarat (PhD 89, currently
with TSMC, San Jose, CA)
Sophie Verdonckt-Vanderbroek (PhD 90, currently
with United Technologies, Penfield, NY)
Cuong Nguyen (PhD 93, currently with CyberTouch,
Kula Lumpar, Malaysia)
Stephen Kuehne (PhD 96, currently with
Lucent Technologies, Orlando, FL)
No current student
The switching speed of today's devices is limited not only by the carrier transit time, but more importantly, also by the parasitic capacitors and resistors. In this project, we develop and model novel transistor structures for high speed applications such as RF communication. Our emphasis is on using advanced processing technologies (e.g., selective silicon epitaxy, wafer bonding, and chemo-mechanical polishing) to significantly reduce parasitic elements.
SOI Power Device and Process
Ying-Keung
Leung (PhD 97, currently with TSMC, Taiwan)
No current student
The integration of power devices with digital and analog electronics promises to revolutionize the power control industry and other related applications. This project explores the performance advantages (breakdown voltage, on resistance, and switching speed) of power devices fabricated on SOI, and develop various processing technologies (e.g., wafer bonding) which are essential to power integrated circuits.
Multilevel Interconnection
Technology
Dave Thomas (PhD 90, currently with IBM
Essex Junction, VT)
Victor Lee (PhD 91, currently with IBM,
Boston, MA)
Ho Kang (PhD 93, currently with Samsung,
Korea)
James Cho (PhD 94, currently with 3Com,
Santa Clara, CA)
Changsup
Ryu (PhD 98, currently with Motorola, Mesa, AZ)
Alvin
Loke (PhD 99, currently with Agilent, Singapore)
Haebum
Lee (PhD 01, currently with Intel, Santa Clara, CA)
Dae-Yong Kim (kimdy@leland.stanford.edu)
Niranjan Talwalkar (narya@stanford.edu)
Interconnection is a critical factor which limits the performance and reliability of today's integrated circuits. The commonly used aluminum alloy is not expected to meet the future requirements. In this project, we develop the technology, and characterize the physical and electrical behavior of multilevel copper interconnections. Current emphasis is on chemical vapor deposition and electroplating techniques. The integration of Cu interconnections with various low-K dielectrics is also under investigation.
Interconnection Design
Patrick
Yue (PhD 98, currently with Atheros Communications, Sunnyvale, CA)
Bendik
Kleveland (PhD 00, currently with Matrix Semiconductor, CA)
Theerachet Soorapanth (chet@leland.stanford.edu)
Richard Chang (rtchang@leland.stanford.edu)
Frank Kolor (fpkolor@leland.stanford.edu)
So-Young Kim
(ksyoung@leland.stanford.edu)
Haitao Gan
(hgan@leland.stanford.edu)
As multiple levels of interconnects are packed in ever-closer proximity, the electromagnetic interactions become significant and affect signal propagation and integrity. Furthermore, at above GHz, high-frequency effects (skin depth, dielectric and substrate losses, etc.) become non-negligible. In this project, the characteristics of copper and low-K dielectrics at above GHz frequencies are studied. Appropriate models are being developed for predicting performance of advanced multilevel interconnect network. The applications of advanced metallization technology to fabricate critical elements such as inductors and strip-lines for RF communication and high speed circuits are also being explore.
Multichip Module Technology
Mark Beiley (PhD 93, currently with Intel,
Chandler, AZ)
Wheling Cheng (PhD 95, currently with nChip,
San Jose, CA)
Justin Leung (PhD 97, currently with Intel,
Santa Clara, CA)
No current student
On and off chip data transmission is a bottleneck of communication in many high speed systems. In this project, we study the utilization of multichip module technology to eliminate the packages and reduce the spatial distances between chips. Testing of the bare chips before they are mounted on the module is widely regarded as the most critical problem plaguing the progress of the industry. Our present emphasis is to develop an active array probe card technology for high speed and high resolution testing of integrated circuits which have a large number of input/output pads.
Optical Interconnects
Abbas Behfar-Rad (PhD 90, currently with
IBM, East Fishkill, NY)
Steve Biellak (PhD 95, currently with Tencor
Instruments, Mountain View, CA)
No current student
Optical interconnection is expected to play a major role in data communication within and between multichip modules. This project aims at developing GaAs/AlGaAs lasers and appropriate interfacing techniques to achieve optical interconnections between chips. The work emphasizes the monolithic fabrication of laser structures.
Wafer
Scale DSP System
Jaehee You (PhD 90, currently with Hongik
University, Seoul, Korea)
No current student
In this project, a pipelined digital signal processing system is designed with systolic array approach for multichip module.
